The present invention relates in general to an apparatus for receiving an incoming stream of a SONET (Synchronous Optical NETwork) payload envelope (SPE) and, more particularly, to a microcontroller for controlling a circuit that provides a desynchronized clock for smoothly adapting the rate at which DS-N data is retrieved from a data buffer to the rate at which the incoming SONET data is stored in the data buffer.
In telephone communications, in the past, data was carried exclusively over metallic media such as twisted pair and coaxial cable. Over metallic media, data is transferred at a speed or line rate of various levels. For example, the human voice can be carried as a digital signal at a line speed of 64 kilobits per second (kbps). For this line speed, the voice signal must be sampled 8,000 times each second, and using pulse code modulation, each voice value is carried as an eight-bit sample. This 64 kbps rate is called the Digital Signal level 0, or DS-0, rate. Higher rates, such as DS-1, DS-2, DS-3, . . . DS-N also exist, and are described in the International Telegraph and Telephone Consultative Committee (CCITT) Recommendations G.703. However, the speed at which data is transferred over metallic media is limited. To overcome this limitation, optical fiber media have been developed, which can accommodate much higher line speeds, and hence can transfer much more information in a given period of time.
For optical fiber transmission systems, the SONET standard defines a line rate hierarchy and frame format. SONET is an American National Standards Institute (ANSI) specification for a high-speed digital hierarchy for optical fiber communications, and is described in detail in ANSI T1.105 and T1.106.
The SONET TDM hierarchy is based upon transmission building blocks of 51.84 million bits per second (Mbps) each. The 51.84 Mbps rate is called the Synchronous Transport Signal level 1 (STS-1). Subsequent rates or levels STS-N are all multiples of the basic rate of 51.84 Mbps, for example, the STS-3 rate is 155.52 Mbps.
The basic unit of transport is the STS-1 frame, which as shown in FIG. 1, is organized into nine rows of 90 bytes or 810 bytes per frame. Each frame is generated 8,000 times per second (8 kHz), thus, yielding the 51.S4 Mbps STS-1 rate (i.e., 8000 frames/second * 810 bytes/frame * 8 bits/byte).
The first three columns of each frame provide Transport Overhead (TOH) information for providing operations, administration, maintenance, and provisioning control type functions. The remaining 87 columns (i.e., 873 bytes) include the STS-1 Envelope Capacity or Synchronous Payload Envelope (SPE).
Each row of the SPE begins with a Path Overhead (POH) byte which is also used for operations, administration, maintenance, and provisioning control type functions. The remaining 774 bytes are free for transporting voice/data signals. Although exactly one STS-1 SPE can fit into one STS-1 frame (including the TOH and POH data bytes), an SPE will usually begin in one STS-1 frame and end in the next. In other words, the SPE does not occupy a fixed position within the STS-1 frame, but rather "floats," and thus spans into two frames.
In theory, the frequency of an STS-1 frame should maintain a frequency of 8 KHz throughout the synchronous optical network, (i.e., from source to destination). However, for many reasons including the fact that different regions employ different timing references, SONET connections are not truly synchronous.
The SONET standard, however, provides a ten-bit pointer H1 and H2 as a rate adaption mechanism to compensate for different timing references. That is, the position of the first byte J1 of the SPE within an STS-1 frame is given by the ten-bit pointer H1 and H2, which is transferred in the TOH section. The pointer H1 and H2 provides the offset in number of bytes from their position in the TOH section to the first SPE byte J1.
Consider, for example, a SONET multiplexer where an incoming data tributary has a data rate (or frequency) that is higher than its nominal value, which is equivalent to the case where the multiplexer transmits with a frequency lower than the nominal. The tributary data will "pile up" at the multiplexer (i.e., data overrun) since the data from the SONET source is arriving faster than the multiplexer is transmitting it to the DS-N system. To prevent data overruns, the multiplexer will occasionally begin an SPE cycle one byte time earlier than usual. Such an action is referred to as a negative pointer adjustment, and results in the SPE being repositioned one byte earlier than its previous position relative to the STS-1 frame. On the other hand, when the data tributary has a lower than nominal frequency or the multiplexer transmits with a higher than nominal frequency, the multiplexer performs a positive pointer adjustment from time to time to avoid a data underrun.
FIG. 2 shows a block diagram of an "end-to-end" connection of DS-N type equipment. There is shown a transmitter which includes DS-N type equipment coupled to a SONET transmitter which includes a DS-N synchronizer and an Optical Interface. The SONET transmitter is coupled by optical fiber to a SONET receiver, which is composed of an optical interface and DS-N desynchronizer, the desynchronizer being the focus of the invention described herein. Finally, the received and desychronized signal is received by the DS-N type receiving equipment.
In more specific terms, the transmitting equipment maps a DS-N signal to a SONET SPE portion of an STS-N frame, which is commonly referred to as "asynchronous DS-N mapping." The synchronizer synchronizes the operation of the connected DS-N equipment to the SONET equipment. On the other hand, the desynchronizer circuit on the receiving side recovers the DS-N signal from the SPE within the STS-N frame.
As an example, the asynchronous mapping standard for a DS-3 signal to a STS-1 signal provides a rate adaption mechanism for compensating for the different tolerances between the SPE at the STS-1 rate and the DS-3 rate. That is, a DS-3 signal has a nominal bit rate of 44.736000 Mbps, with a tolerance of .+-.20 ppm, whereas, the STS-1 signal has a nominal bit rate of 51.840000 Mbps, with a tolerance of .+-.4.7 ppm.
To adapt the DS-3 signal to the STS-1 signal, stuff bits (S-bits) are provided in each row of the SPE. Therefore, on average, the synchronizer will stuff two out of three bits, that is, one out of every three bits will contain DS-3 data that must be recovered to properly adapt the DS-3 signal to the STS-1 signal.
On the receiving end, the desynchronizer must recover or extract the DS-N data from the SPE of the STS-1 frame and provide the same to the DS-N equipment. In so doing, the desynchronizer must minimize jitter and avoid, if possible, buffer spills (i.e., data overrun and underruns) which occur when the receiving equipment is unable to match the frequency of its desynchronization clock to the rate of the incoming DS-N data. As stated above, buffer spills can occur due to SONET lines connected between different regions employing different timing references.
Jitter results because of at least two factors. First, the variation in the S-bit stuffing ratio and by pointer H1 and H2 adjustments. Both of these factors contribute to the variation in the rate at which the data buffer fills and empties, which in turn causes the desynchronizer to speed up or slow down.
It is, therefore, a function of the desynchronization circuit to smoothly adapt the rate of the outputted DS-N data sent to the DS-N type receiving equipment to the rate of the incoming SONET SPE data.
Desynchronizers which recover DS-N data from an SPE are known. For example, U.S. Pat. No. 4,996,698 to Nelson shows an apparatus for and method of integrating large phase hit error signals (which occur due to pointer adjustments) in a clock smoothing process to reduce jitter in the smoothed clock output. Nelson discloses a high pass filter and a summing circuit for filtering the large phase hit signal, and summing it with a periodically discontinuous clock. The summed result is then applied to a phase detector and second filter to produce a control signal which is applied to a voltage controlled oscillator. The output of the voltage controlled oscillator provides a continuous clock signal representing the smoothed clock.
The desynchronizer disclosed in Nelson, however, presents several disadvantages. First, because Nelson employs a voltage controlled oscillator for a frequency source, a low level of intrinsic phase noise (i.e., jitter) is hard to achieve. Second, the voltage controlled oscillator does not permit very fine resolution control of the frequency in comparison to a digital frequency control device, nor does it permit very precise frequency tuning. Finally, a voltage controlled oscillator requires "tweaking" at the time of manufacture, whereas a digital implementation does not.
U.S. Pat. No. 4,941,156 to Stern et al. relates to a jitter attenuation circuit. Specifically, Stern et al. discloses a FIFO which receives data that is synchronized with a write clock and puts out data in synchronism with a read clock. The read clock is synchronized with the write clock by a phase locked loop. The phase locked loop contains a digitally controlled linear oscillator, wherein the phase detector provides a quantized output to incrementally step the digitally controlled oscillator up or down in frequency to track the write clock while attenuating jitter.
The circuit disclosed in Stern et al. generally has similar disadvantages as the apparatus disclosed in Nelson. Furthermore, the digitally controlled oscillator is responsive to only the difference between the write address and read address, which does not provide an acceptable response to SONET data transmission circuits, particularly with large phase hit errors (i.e., pointer adjustments).